1. Field of the Invention
This invention relates to a semiconductor device and the manufacturing method thereof, and in particular, to magnetic random access memory (MRAM) wherein a mechanism for storing information xe2x80x9c1xe2x80x9d and xe2x80x9c0xe2x80x9d by taking advantage of tunnel magneto resistive (TMR) effects is utilized as a memory cell, and also to the manufacturing method thereof.
2. Description of the Related Art
In recent years, there has been proposed a MRAM utilizing, as an information memory element, a tunneling magneto resistive element (hereinafter, referred to simply as a TMR element).
This TMR element is formed of a structure wherein a thin tunneling insulating film is sandwiched between a couple of magnetic films. Further, this TMR element is enabled to take two states, i.e. a state wherein the directions of the spins of this couple of magnetic films are the same and parallel with each other, and another state wherein the directions of the spins of these magnetic films are counter-parallel with each other.
When the directions of the spins of these magnetic films are the same and parallel with each other, the tunneling resistance of current flowing through the tunneling insulating film becomes the lowest, thereby enabling the TMR element to memorize xe2x80x9c1xe2x80x9d under this condition. On the other hand, when the directions of the spins of these magnetic films are counter-parallel with each other, the tunneling resistance of current flowing through the tunneling insulating film becomes the highest, thereby enabling the TMR element to memorize xe2x80x9c0xe2x80x9d under this condition.
Next, the principle of operation of this TMR element will be briefly explained. When it is desired to write the xe2x80x9c1xe2x80x9d and xe2x80x9c0xe2x80x9d data in this TMR element, a couple of word line and data line are selected, and an electric current is delivered to them to generate a magnetic field. As a result, a magnetic field is applied to a TMR element of the selected cell located at the cross-point between the word line and the data line, so that the xe2x80x9c1xe2x80x9d and xe2x80x9c0xe2x80x9d data are enabled to be written therein as the magnetic field exceeds over the reversing threshold value of the spin of this TMR element. On the other hand, if the xe2x80x9c1xe2x80x9d and xe2x80x9c0xe2x80x9d data written in this TMR element are to be read out, an electric current is delivered to read out a difference in resistance of the tunneling insulating film between different TMR elements, thereby determining if the data is xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d.
The MRAM memory utilizing this conventional TMR element is accompanied with the following problems. Namely, since this conventional TMR element is constructed such that an electric current is delivered through a tunneling insulating film, a fluctuation in resistance between different TMR elements is caused to increase logarithmically as the film thickness of the tunneling insulation film is increased. Since the film thickness of the tunneling insulating film of the TMR element that has been reported to date varies within the range of about several to several tens angstroms, the resistance between the TMR elements will be scattered, depending on the scattering in thickness of the tunneling insulating film.
Therefore, if the MRAM is desired to be formed through the application of a differential sense amplifier system where data is designed to be read through a comparison of the resistance value of the tunneling insulating film with a reference value as employed in the DRAM, the variation of resistance xcex94R to be determined by the magneto resistive ratio (hereinafter, referred to as MR ratio) due to the TMR is required to be larger than the scattering of the reference resistance or than the scattering of resistance between the TMR elements. However, since the MR ratio reported to date is at most 50% or so, the variation of resistance xcex94R cannot be made sufficiently large.
In order to overcome the aforementioned problems, the following system, for example, has been conventionally adopted.
FIG. 34 shows a cross-sectional view of a semiconductor memory device according to the prior art. FIG. 35 shows an equivalent circuit of the semiconductor memory device according to the prior art.
As shown in FIG. 34, a plurality of TMR elements 71 disposed inside a memory cell are respectively connected with a pair of switching transistors 72, thus constituting one unit 73. If data is to be read out, the switching transistor 72 located only at the cell selected is turned ON, thereby permitting an electric current to flow from data lines 74 and 75 to the ground. However, if it is tried, with the employment of this structure, to compare the resistance value of the TMR element 71 with that of the reference cell, not only the scattering of tunneling resistance of the TMR element 71 but also the scattering of channel resistance of the switching transistor 72 is required to be taken into account for the comparison. Therefore, it becomes impossible to secure a sufficient MR ratio, thereby making it difficult to employ the differential sense amplifier system.
Therefore, conventionally proposed has been a structure wherein a pair of the units 73 each constituted by the TMR element 71 and the switching transistor 72 are combined into a single memory cell 76 as shown in FIG. 35. In this case, the circuit thereof is constructed in such a manner that the opposite data of xe2x80x9c1xe2x80x9d and xe2x80x9c0xe2x80x9d are always written in these two TMR elements 71. As a result, the variation of resistance xcex94R to be determined by the MR ratio can be doubled, thereby making it possible to perform the read/write operation of an MRAM memory cell, while enabling a sufficient margin to be secured for determining the xe2x80x9c1xe2x80x9d and xe2x80x9c0xe2x80x9d data.
However, this conventional structure is accompanied with a problem that since the units 73 are employed for constituting a single memory cell 76, four elements, i.e. two TMR elements 71+two of MOS transistors 72 are required to be included in each bit of the memory cell 76, this conventional structure is disadvantageous in increasing the area of the memory cell 76. Additionally, even though it is certainly possible to double the margin for determining the xe2x80x9c1xe2x80x9d and xe2x80x9c0xe2x80x9d data, it can not necessarily be said that a sufficient margin can be secured for reading data.
According to a first aspect of this invention, there is provided a semiconductor memory device, which comprises: first memory elements to store a first state or a second state according to a change in resistance value, each of the first memory elements comprising one terminal and the other terminal, the first memory elements arranged parallel with each other; a first wiring connected with the one terminal of each of the first memory elements; and a second wiring formed in parallel with the first wiring and connected with the other terminal of each of the first memory elements; wherein the first state or the second state stored in one of selected from the first memory elements is read out by delivering an electric current from one of the first and second wirings via the one of selected from the first memory elements to the other of the first and second wirings.